The general trend in semiconductor technology toward increasing device integration has produced chips that have one million or more individual devices on them. With this increasing integration has come the challenge of interconnecting these devices so that they can form circuits that have acceptable signal propagation delays. As a greater number of devices are coupled to a given interconnection line, the cumulative resistive load that the line must drive produces corresponding increases in driving currents and signal propagation delays. In order to reduce these driving currents and delays, the industry has explored and implemented various means of decreasing the resistive load on these interconnecting lines.
One very effective way of reducing the resistive load is to form a refractory metal silicide between the interconnecting line and the device or surface to be coupled thereto. A silicide is formed by the reaction of a refractory metal (e.g. tungsten, titanium, molybdenum, nickel, tantalum, cobalt, etc.) and silicon. The resulting refractory metal silicide produces a characteristic resistance that is much lower than that achieved using conventional metals or doped polysilicon.
One particularly efficient use of refractory metal silicides is the so-called "salicide" process. In this process, the source, gate and drain electrodes of a field effect transistor are formed using conventional techniques. Then a blanket layer of refractory metal is applied, and the substrate is heated. During this heating (or "sintering") cycle, silicon will diffuse upward from areas in which the refractory metal contacts either the monocrystalline silicon substrate (e.g., the diffused source/drain regions) or the exposed polycrystalline silicon regions (e.g., the upper surface of the gate electrode) to form a silicide above these areas. At the same time, although some silicon diffuses upward from those areas in which the refractory metal overlays silicon oxide (e.g., silicon oxide isolation structures, as well as silicon oxide "spacers" that are formed on the sidewalls of the gate electrode), the diffusion rate is slow enough so that typically no silicide is formed in these regions during the sintering cycle. After the sintering cycle is completed, the structure is exposed to an etchant (typically a wet etchant) that preferentially attacks the unreacted refractory metal without appreciably attacking the reacted silicide. The term "salicide" refers to the end product of this process: regions of silicide that are aligned to and in contact with the source/drain regions (to thus lower the contact resistance) and the gate electrode (to thus lower the gate sheet resistance) of the FET, without the use of a separate mask-and-etch step to selectively provide silicide in these areas.
In an article by Murarka et al, entitled "Refractory Silicides For Low Resistivity Gates and Interconnects," IEDM Technical Digest 1979, Paper 20.1, pp. 454-457, the general methods of forming silicides (i.e., sputtering or evaporating the silicide from a single source, sputtering or evaporating refractory metal and silicon from separate sources, and sputtering or evaporating the refractory metal on exposed silicon) are reviewed. The article includes a graph that shows the sheet resistance of titanium silicide formed by deposition and sintering of titanium on polysilicon as being approximately one ohm/square at sintering temperatures of 700.degree. C.-1000.degree. C.
An article by Roberts, entitled "Salicide Process For Silicide Wiring By CVD," IBM Technical Disclosure Bulletin, Vol. 26, No. 8, January 1984,p. 4338, discloses a salicide process using a low-rate tungsten deposition, such that a low sintering temperature (650.degree. C.-700.degree. C.) may be used. This lower temperature prevents a phenomena referred to as "bridging" that will be discussed in more detail below.
An article by Jones et al, entitled "Salicide With Buried Silicide Layer," IBM Technical Disclosure Bulletin, Vol. 27, No. 2, July 1984,pp. 1044-1045, discloses a salicide process in which a fresh layer of silicon is formed over the gate electrode prior to further processing. This permits a salicide process to be carried out on a silicide gate electrode by adding more silicon for reaction.
An article by Ting, "Silicide For Contacts And Interconnects," IEDM Technical Digest 1984, Paper 5.1, pp. 110-113, describes the use of silicides for diffused contacts, for gate electrodes, and for both (i.e., salicide processing). In salicide applications, Ting notes out that the sintering temperature for TiSi.sub.2 should be kept at 600.degree.-700.degree. C. in order to prevent bridging. Moreover, the article points out that titanium silicide should be formed in a nitrogen atmosphere, in order to further prevent bridging.
An article by Okabayashi et al, entitled "Low-Resistance MOS Technology Using Self-Aligned Refractory Silicidation," IEEE Transactions On Electron Devices, Vol. ED31, No. 9, September 1984 pp. 1329-1334, describes a process of silicide formation in which an inert ion beam is used after molybdenum is applied to a silicon surface in order to promote intermixing at the metal-silicon interface. This intermixing will reduce the anneal time of the subsequent silicide reaction, to thus prevent an excessive amount of lateral silicon diffusion.
An article by Haken, entitled "Application of the Self-Aligned Titanium Silicide Process to Very Large-Scale Integrated N-Metal-Oxide-Semiconductor and Complementary Metal-Oxide-Semiconductor Technologies," Journal of Vacuum Science and Technology, Vol. 3, No. 6, November/December 1985, pp. 1657-1663, discusses the attributes of titanium silicide in a salicide process. The paper recites the general salicide process disclosed in the Ting article, and discusses the importance of TiN in preventing silicon outdiffusion.
U.S. Pat. No. 4,180,596 (issued Dec. 25, 1979 to Crowder et al and assigned to the assignee of the invention) discloses a process of forming a silicide wherein the silicon and the refractory metal are co-evaporated from separate sources. The refractory metals discussed are tungsten, molybdenum, tantalum and rhodium.
U.S. Pat. No. 4,332,839 (issued June 1, 1982 to Levinstein et al and assigned to AT&T) discloses a process of forming titanium silicide wherein the titanium is sintered in a H.sub.2 atmosphere at 900.degree. C.
U.S. Pat. No. 4,337,476 (issued June 29, 1982 to Fraser et al and assigned to AT&T) discloses a process for forming a silicon-rich titanium silicide (i.e., TiSi.sub.x, x&gt;2) by varying the sputtering rates of the respective targets.
U.S. Pat. No. 4,545,116 (issued 10/8/1985 to Lau et al and assigned to Texas Instruments) discloses a process of forming a titanium silicide, wherein the titanium metal is sintered in a nitrogen atmosphere at a temperature of about 625.degree. C. so as to prevent the lateral diffusion of silicon during the titanium silicide forming process.
As is apparent from the above art, it is generally known that during sintering of the refractory metal and silicon, silicon will diffuse laterally to form a silicide "bridge" in regions other than where it is desired. As shown in FIG. 1 (Prior Art), when a refractory metal 14 such as titanium is deposited on a substrate 10 having a silicon oxide layer 12 thereon, the objective is to form a titanium silicide layer 14A having a lateral length A (i.e., so that the TiSi.sub.2 layer 14A is completely self-aligned with respect to the portion of substrate 10 that is exposed by silicon oxide layer 12). However, in titanium silicide reactions, silicon is the active specie. The diffusion of silicon is not directionally limited. Thus, during sintering, silicon will diffuse laterally and react with a portion of the refractory metal 14 not immediately above the exposed portion of the substrate 10. The net effect is to produce a silicide region having a lateral length of A+X.
Ordinarily, this increase in lateral length is not a debilitating problem. However, in the salicide process wherein a refractory metal is coated over a gate electrode of an FET, this problem greatly increases in importance. As shown in FIG. 2 (Prior Art), in addition to forming silicide regions 14A on either side of gate electrode 20A as well as on top of gate electrode 20, enough silicon may laterally diffuse so that silicide regions 14A' are formed on top of the silicon oxide gate electrode sidewalls 20A. These undesired "bridging" silicide regions will effectively render the FET useless by shorting together the source, gate, and drain electrodes.
As pointed out in the Ting and Haken papers and the Lau patent, this "bridging" phenomena can be avoided by the use of one or more techniques. One technique is to decrease the sintering temperature from 900.degree. C. to approximately 600.degree.-700.degree. C. (i.e., the minimum temperature at which the metal and the silicon will react to form a silicide). There will be less silicon diffusion at the lower temperature. Another technique is to carry out the sintering operation in a nitrogen (N.sub.2) gas atmosphere ambient. As shown in FIG. 3 (Prior Art), the nitrogen will react with the exposed surface of the titanium to form titanium nitride (TiN) 16. Since the nitrogen will diffuse more quickly into the titanium than will the silicon, the portions of the refractory metal that are susceptible to forming lateral silicide regions will be converted to TiN before the silicon can laterally diffuse to form a bridging region. Thus the silicide regions 14A will have less of a lateral portion extending above oxide layer 12. A subsequent wet etchant will remove the titanium nitride without appreciably attacking the titanium silicide. As discussed in the Ting article, the ideas of lower temperatures and a nitrogen atmosphere may be used in tandem to further reduce the lateral diffusion of silicon during the formation of a silicide region.
In dense one-device trench memory cells such as that described in the above-mentioned U.S. patent application Ser. No. 626,512, a transfer gate FET is used to access the trench storage capacitor. The doped polysilicon within the trench is separated by a layer of dielectric from the remainder of the substrate. The dielectric extends to the surface of the substrate, such that the upper surfaces of the source electrode of the FET and the poly-filled trench are separated by the dielectric. In order to couple the source electrode of the FET to the doped polysilicon within the trench, as described in the patent application a conductive material must be deposited and etched to form a contact above the source electrode and the poly-filled trench by bridging the dielectric therebetween.
The above-described process of forming the bridge contact is inefficient, in that a separate layer must be masked and etched. This adds to process expense and reduces circuit density. Thus, it would be advantageous to provide some means of connecting the source electrode to the poly-filled trench without the use of a separate mask-and-etch step.